In an imaging device such as a still-image camera or a moving-image camera, various image processing is performed by an image processing device such as a mounted system LSI. In many image processing devices mounted on an imaging device, a plurality of functional blocks configured to perform image processing are provided and are connected to an internal data bus. Also, in the image processing device, for example, a dynamic random access memory (DRAM) which is a storage device configured to temporarily store image data to be subjected to image processing is connected. The DRAM is connected to a data bus inside the image processing device and shared by functional blocks connected to the data bus. In such an image processing device, each functional block operates as a data transfer device configured to perform the transfer of image data to and from the DRAM, i.e., the reading of image data to be subjected to image processing from the DRAM or the writing of image data to the DRAM after the image processing according to a direct memory access (DMA) transfer via the data bus.
In the image processing device, a bus arbiter for arbitrating the DMA transfer of each functional block (a data transfer device) to and from the DRAM is provided. The bus arbiter arbitrates an access request (hereinafter referred to as a “DMA request”) based on the DMA transfer output from each functional block and controls access to the DRAM by the functional block receiving the DMA request. To maximize the efficiency of the DMA transfer, the arbitration of the DMA request by the bus arbiter reduces a loss time during which the DRAM cannot accept the access (for example, a bank loss time related to a bank, a reading/writing switching loss time related to switching between the reading of data and the writing of data, or the like) and is performed on the basis of a priority set for each functional block in accordance with a predetermined condition. That is, the bus arbiter arbitrates the DMA request from each functional block to preferentially receive a DMA request from a functional block with a high priority.
Each functional block (a data transfer device) provided in the image processing device is also configured to include a DMA buffer with a predetermined storage capacity in consideration of a case in which an output DMA request is not accepted by the bus arbiter. In a functional block having a configuration including the DMA buffer, a predetermined amount of image data to be subjected to image processing is acquired according to the DMA transfer (reading from the DRAM) and pre-stored in the DMA buffer, and image processing is performed while the image data stored in the DMA buffer is read at a timing when necessary thereafter. In the functional block including the DMA buffer, a subsequent DMA request is output in accordance with a free capacity of the DMA buffer. Thereby, in the functional block including the DMA buffer, the image data can be transferred at a desired transfer rate according to the DMA transfer, and the image processing can be completed during a predetermined period.
Meanwhile, in the functional block (the data transfer device) having the configuration including the above-described DMA buffer, there are a period during which the DMA transfer is frequently performed and a period during which the DMA transfer is seldom performed in the process of image processing. This is because the functional block having the configuration including the DMA buffer continues to successively output DMA requests from an initial timing at which the image processing starts until the storage capacity of the DMA buffer is in a full state and outputs the DMA request only when the storage capacity of the DMA buffer is in a free state if the storage capacity of the DMA buffer is in the full state. Here, in the functional block (the data transfer device) including the DMA buffer, a period during which the DMA request continues to be successively output until the storage capacity of the DMA buffer is in the full state is a period during which the DMA transfer is frequently performed and a period during which the DMA request is output only when the storage capacity of the DMA buffer is in the free state is a period during which the DMA transfer is seldom performed.
Thus, in a system including a functional block (a data transfer device) having a configuration including a DMA buffer as described above, a system operation, i.e., an operation of an image processing device or an imaging device equipped with the image processing device, may fail according to a priority preset for arbitrating the DMA request from each functional block. For example, when the priority is set for each functional block, the system operation may fail if a high priority is set for a functional block having a configuration including a DMA buffer in accordance with a period during which the DMA transfer is frequently performed. This is because, if a functional block having a configuration including a DMA buffer for which a high priority is set continues to successively output DMA requests during a period when the DMA transfer is frequently performed, i.e., if the DMA requests are output in a concentrated manner, the DMA request of another functional block with a low priority is not accepted and the functional block with the low priority cannot perform the DMA transfer. In contrast, for example, when the priority is set for a functional block having a configuration including a DMA buffer, if a low priority is set for a functional block of a configuration including a DMA buffer in accordance with a period during which the DMA transfer is seldom performed, i.e., if a high priority is set for another functional block, the DMA transfer cannot be performed during a period in which the functional block of the configuration including the DMA buffer frequently performs the DMA transfer and the system operation may fail as expected.
Therefore, a setting process for sequentially changing the priority in consideration of each of a period during which the DMA transfer is frequently performed and a period during which the DMA transfer is seldom performed in the functional block (the data transfer device) of the configuration including the DMA buffer is conceived. However, the number of functional blocks (data transfer devices) having the DMA buffer is not limited to one in the system, and a process when the priority is set for each functional block becomes more complex as the number of functional blocks with a configuration including the DMA buffer included in the system becomes larger. Also, if the temporarily determined setting of the priority is changed, i.e., if it is necessary to change a condition when the priority is set, the change in the condition can cause a failure of a system operation.
In this manner, in a system including a functional block (a data transfer device) having a configuration including a DMA buffer, even when a DMA request is arbitrated on the basis of a preset priority for each functional block, a system operation may fail according to a setting of a priority for each functional block.
Therefore, for example, as in Japanese Unexamined Patent Application, First Publication No. 2006-039672, technology for alleviating the concentration of DMA requests from a specific functional block (a bus master) has been disclosed. In Japanese Unexamined Patent Application, First Publication No. 2006-039672, a method of controlling the right to use a bus so that a bus master having a high priority does not exclusively occupy the right to use the bus is disclosed. More specifically, in Japanese Unexamined Patent Application, First Publication No. 2006-039672, technology in which an interval predetermined for each DMA request output by the bus master is available so that the DMA transfer in another functional block is not inhibited when a bus master with a high priority successively outputs DMA requests is disclosed. In other words, according to the technology disclosed in Japanese Unexamined Patent Application, First Publication No. 2006-039672, a functional block (a bus master) for which the output DMA request is accepted by the bus arbiter does not output the next DMA request until a predetermined time elapses and therefore DMA requests from functional blocks (bus masters) with the high priority are not concentrated. Thereby, a DMA request output during a period until a predetermined time elapses can also be accepted for a functional block (a bus master) having a low priority.